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Features
* High-performance, Low-power AVR(R) 8-bit Microcontroller * Advanced RISC Architecture
- 131 Powerful Instructions - Most Single-clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation - Up to 16 MIPS Throughput at 16 MHz - On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories - 16K Bytes of In-System Self-Programmable Flash Endurance: 10,000 Write/Erase Cycles - Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation - 512 Bytes EEPROM Endurance: 100,000 Write/Erase Cycles - 1K Byte Internal SRAM - Programming Lock for Software Security JTAG (IEEE std. 1149.1 Compliant) Interface - Boundary-scan Capabilities According to the JTAG Standard - Extensive On-chip Debug Support - Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features - Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes - One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode - Real Time Counter with Separate Oscillator - Four PWM Channels - 8-channel, 10-bit ADC 8 Single-ended Channels 7 Differential Channels in TQFP Package Only 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x - Byte-oriented Two-wire Serial Interface - Programmable Serial USART - Master/Slave SPI Serial Interface - Programmable Watchdog Timer with Separate On-chip Oscillator - On-chip Analog Comparator Special Microcontroller Features - Power-on Reset and Programmable Brown-out Detection - Internal Calibrated RC Oscillator - External and Internal Interrupt Sources - Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby I/O and Packages - 32 Programmable I/O Lines - 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF Operating Voltages - 2.7 - 5.5V for ATMEGA16L - 4.5 - 5.5V for ATmega16 Speed Grades - 0 - 8 MHz for ATMEGA16L - 0 - 16 MHz for ATmega16 Power Consumption @ 1 MHz, 3V, and 25C for ATMEGA16L - Active: 1.1 mA - Idle Mode: 0.35 mA - Power-down Mode: < 1 A
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8-bit Microcontroller with 16K Bytes In-System Programmable Flash ATmega16 ATMEGA16L Summary
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2466NS-AVR-10/06
Note: This is a summary document. A complete document is available on our Web site at www.atmel.com.
Pin Configurations
Figure 1. Pinout ATmega16
PDIP
(XCK/T0) PB0 (T1) PB1 (INT2/AIN0) PB2 (OC0/AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1A) PD5 (ICP1) PD6 PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3) PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF GND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 (TDI) PC4 (TDO) PC3 (TMS) PC2 (TCK) PC1 (SDA) PC0 (SCL) PD7 (OC2)
TQFP/QFN/MLF
PB4 (SS) PB3 (AIN1/OC0) PB2 (AIN0/INT2) PB1 (T1) PB0 (XCK/T0) GND VCC PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3)
(MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2
PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF GND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 (TDI) PC4 (TDO)
Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.
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ATmega16(L)
2466NS-AVR-10/06
(INT1) (OC1B) (OC1A) (ICP1) (OC2)
NOTE: Bottom pad should be soldered to ground.
PD3 PD4 PD5 PD6 PD7 VCC GND (SCL) PC0 (SDA) PC1 (TCK) PC2 (TMS) PC3
ATmega16(L)
Overview
The ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2. Block Diagram
PA0 - PA7 VCC PC0 - PC7
Block Diagram
PORTA DRIVERS/BUFFERS
PORTC DRIVERS/BUFFERS
GND
PORTA DIGITAL INTERFACE
PORTC DIGITAL INTERFACE
AVCC
MUX & ADC
AREF PROGRAM COUNTER
ADC INTERFACE
TWI
STACK POINTER
TIMERS/ COUNTERS
OSCILLATOR
PROGRAM FLASH
SRAM
INTERNAL OSCILLATOR XTAL1
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS X
WATCHDOG TIMER
OSCILLATOR
XTAL2 MCU CTRL. & TIMING RESET
INSTRUCTION DECODER
Y Z
CONTROL LINES
ALU
INTERRUPT UNIT
INTERNAL CALIBRATED OSCILLATOR
AVR CPU
STATUS REGISTER
EEPROM
PROGRAMMING LOGIC
SPI
USART
+ -
COMP. INTERFACE
PORTB DIGITAL INTERFACE
PORTD DIGITAL INTERFACE
PORTB DRIVERS/BUFFERS
PORTD DRIVERS/BUFFERS
PB0 - PB7
PD0 - PD7
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2466NS-AVR-10/06
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega16 provides the following features: 16K bytes of In-System Programmable Flash Program memory with Read-While-Write capabilities, 512 bytes EEPROM, 1K byte SRAM, 32 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, Internal and External Interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain (TQFP package only), a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next External Interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmel's high density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega16 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATmega16 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
Pin Descriptions
VCC GND Port A (PA7..PA0) Digital supply voltage. Ground. Port A serves as the analog inputs to the A/D Converter. Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.
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ATmega16(L)
2466NS-AVR-10/06
ATmega16(L)
Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega16 as listed on page 56. Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset occurs. Port C also serves the functions of the JTAG interface and other special features of the ATmega16 as listed on page 59. Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega16 as listed on page 61. RESET Reset Input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page 36. Shorter pulses are not guaranteed to generate a reset. Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Output from the inverting Oscillator amplifier. AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. AREF is the analog reference pin for the A/D Converter. A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.
XTAL1 XTAL2 AVCC
AREF
Resources
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2466NS-AVR-10/06
Register Summary
Address
$3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31(1) ($51)(1) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20(2) ($40)(2) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) $07 ($27) $06 ($26) $05 ($25) $04 ($24) $03 ($23) $02 ($22)
Name
SREG SPH SPL OCR0 GICR GIFR TIMSK TIFR SPMCR TWCR MCUCR MCUCSR TCCR0 TCNT0 OSCCAL OCDR SFIOR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 ASSR WDTCR UBRRH UCSRC EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR UCSRA UCSRB UBRRL ACSR ADMUX ADCSRA ADCH ADCL TWDR TWAR
Bit 7
I -
Bit 6
T -
Bit 5
H -
Bit 4
S - SP4 - - OCIE1A OCF1A RWWSRE TWSTO SM0 JTRF COM00
Bit 3
V - SP3 - - OCIE1B OCF1B BLBSET TWWC ISC11 WDRF WGM01
Bit 2
N SP10 SP2 - - TOIE1 TOV1 PGWRT TWEN ISC10 BORF CS02
Bit 1
Z SP9 SP1 IVSEL - OCIE0 OCF0 PGERS - ISC01 EXTRF CS01
Bit 0
C SP8 SP0 IVCE - TOIE0 TOV0 SPMEN TWIE ISC00 PORF CS00
Page
7 10 10 83 46, 67 68 83, 114, 132 84, 115, 132 250 178 30, 66 39, 67, 229 81 83 28 225
SP7 SP6 SP5 Timer/Counter0 Output Compare Register INT1 INTF1 OCIE2 OCF2 SPMIE TWINT SM2 JTD FOC0 INT0 INTF0 TOIE2 TOV2 RWWSB TWEA SE ISC2 WGM00 INT2 INTF2 TICIE1 ICF1 - TWSTA SM1 - COM01
Timer/Counter0 (8 Bits) Oscillator Calibration Register On-Chip Debug Register ADTS2 COM1A1 ICNC1 ADTS1 COM1A0 ICES1 ADTS0 COM1B1 - - COM1B0 WGM13 ACME FOC1A WGM12 PUD FOC1B CS12 PSR2 WGM11 CS11 PSR10 WGM10 CS10
55,86,133,199,219 109 112 113 113 113 113 113 113 114 114
Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte Timer/Counter1 - Output Compare Register A High Byte Timer/Counter1 - Output Compare Register A Low Byte Timer/Counter1 - Output Compare Register B High Byte Timer/Counter1 - Output Compare Register B Low Byte Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 Timer/Counter2 (8 Bits) Timer/Counter2 Output Compare Register - - URSEL URSEL - - - - UMSEL - - - - UPM1 - - WDTOE - UPM0 - USBS - - AS2 WDE TCN2UB WDP2 UCSZ1 OCR2UB WDP1 UBRR[11:8] UCSZ0 - UCPOL EEAR8 TCR2UB WDP0
127 129 129 130 41 165 164 17 17 17
EEPROM Address Register Low Byte EEPROM Data Register - PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 PORTC7 DDC7 PINC7 PORTD7 DDD7 PIND7 SPI Data Register SPIF SPIE RXC RXCIE ACD REFS1 ADEN WCOL SPE TXC TXCIE ACBG REFS0 ADSC - DORD UDRE UDRIE ACO ADLAR ADATE - MSTR FE RXEN ACI MUX4 ADIF - CPOL DOR TXEN ACIE MUX3 ADIE - CPHA PE UCSZ2 ACIC MUX2 ADPS2 - SPR1 U2X RXB8 ACIS1 MUX1 ADPS1 SPI2X SPR0 MPCM TXB8 ACIS0 MUX0 ADPS0 - PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 PORTC6 DDC6 PINC6 PORTD6 DDD6 PIND6 - PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 - PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0
17 64 64 64 64 64 64 65 65 65 65 65 65 140 140 138 161 162 163 165 200 215 217 218 218 180
USART I/O Data Register
USART Baud Rate Register Low Byte
ADC Data Register High Byte ADC Data Register Low Byte Two-wire Serial Interface Data Register TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE
180
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ATmega16(L)
2466NS-AVR-10/06
ATmega16(L)
Address
$01 ($21) $00 ($20)
Name
TWSR TWBR
Bit 7
TWS7
Bit 6
TWS6
Bit 5
TWS5
Bit 4
TWS4
Bit 3
TWS3
Bit 2
-
Bit 1
TWPS1
Bit 0
TWPS0
Page
179 178
Two-wire Serial Interface Bit Rate Register
Notes:
1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debugger specific documentation for details on how to use the OCDR Register. 2. Refer to the USART description for details on how to access UBRRH and UCSRC. 3. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 4. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.
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2466NS-AVR-10/06
Instruction Set Summary
Mnemonics
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k k
Operands
Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k
Description
Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared
Operation
Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd $FF - Rd Rd $00 - Rd Rd Rd v K Rd Rd * ($FF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd $FF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None
#Clocks
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
ARITHMETIC AND LOGIC INSTRUCTIONS
1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1
PC PC + k + 1 PC Z PC k PC PC + k + 1 PC Z PC k PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1
R1:R0 (Rd x Rr) <<
BRANCH INSTRUCTIONS
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ATmega16(L)
2466NS-AVR-10/06
ATmega16(L)
Mnemonics
BRIE BRID MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV Rd, P P, Rr Rr Rd P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b Rd, Z Rd, Z+
Operands
k k Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr
Description
Branch if Interrupt Enabled Branch if Interrupt Disabled Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow.
Operation
if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (Z) R1:R0 Rd P P Rr STACK Rr Rd STACK I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1
Flags
None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V
#Clocks
1/2 1/2 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DATA TRANSFER INSTRUCTIONS
BIT AND BIT-TEST INSTRUCTIONS
CLV SET CLT SEH
Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG
V0 T1 T0 H1
V T T H
1 1 1 1
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2466NS-AVR-10/06
Mnemonics
Operands
Description
Clear Half Carry Flag in SREG No Operation Sleep Watchdog Reset Break
Operation
H0 H
Flags
#Clocks
1 1 1 1 N/A
CLH MCU CONTROL INSTRUCTIONS NOP SLEEP WDR BREAK
(see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-Chip Debug Only
None None None None
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ATmega16(L)
2466NS-AVR-10/06
ATmega16(L)
Ordering Information
Speed (MHz) Power Supply Ordering Code ATMEGA16L-8AC ATMEGA16L-8PC ATMEGA16L-8MC 8 2.7 - 5.5V ATMEGA16L-8AI ATMEGA16L-8AU(1) ATMEGA16L-8PI ATMEGA16L-8PU(1) ATMEGA16L-8MI ATMEGA16L-8MU(1) ATmega16-16AC ATmega16-16PC ATmega16-16MC 16 4.5 - 5.5V ATmega16-16AI ATmega16-16AU(1) ATmega16-16PI ATmega16-16PU(1) ATmega16-16MI ATmega16-16MU(1) Package 44A 40P6 44M1 44A 44A 40P6 40P6 44M1 44M1 44A 40P6 44M1 44A 44A 40P6 40P6 44M1 44M1 Operation Range Commercial (0oC to 70oC)
Industrial (-40oC to 85oC)
Commercial (0oC to 70oC)
Industrial (-40oC to 85oC)
Note:
1. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
Package Type 44A 40P6 44M1 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
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2466NS-AVR-10/06
Packaging Information
44A
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 11.75 9.90 11.75 9.90 0.30 0.09 0.45 NOM - - 1.00 12.00 10.00 12.00 10.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 12.25 10.10 12.25 10.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 44A REV. B
R
12
ATmega16(L)
2466NS-AVR-10/06
ATmega16(L)
40P6
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
A1
C eB
0 ~ 15
REF
SYMBOL A A1 D E E1 B
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 52.070 15.240 13.462 0.356 1.041 3.048 0.203 15.494 NOM - - - - - - - - - - 2.540 TYP MAX 4.826 - 52.578 15.875 13.970 0.559 1.651 3.556 0.381 17.526 Note 2 Note 2 NOTE
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
B1 L C eB e
09/28/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 40P6 REV. B
R
13
2466NS-AVR-10/06
44M1
D
Marked Pin# 1 ID
E
SEATING PLANE
TOP VIEW
A1 A3
K L D2
Pin #1 Corner
A
SIDE VIEW
1 2 3
Option A
Pin #1 Triangle
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL
Option B
Pin #1 Chamfer (C 0.30)
E2
MIN 0.80 -
NOM 0.90 0.02 0.25 REF
MAX 1.00 0.05
NOTE
A A1 A3 b
0.18 6.90 5.00 6.90 5.00
0.23 7.00 5.20 7.00 5.20 0.50 BSC
0.30 7.10 5.40 7.10 5.40
K b e
Option C
D
Pin #1 Notch (0.20 R)
D2 E E2 e
BOTTOM VIEW
Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3.
L K
0.59 0.20
0.64 0.26
0.69 0.41
5/27/06 2325 Orchard Parkway San Jose, CA 95131 TITLE 44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead Pitch 0.50 mm, 5.20 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 44M1 REV. G
R
14
ATmega16(L)
2466NS-AVR-10/06
ATmega16(L)
Errata
ATmega16(L) Rev. M
The revision letter in this section refers to the revision of the ATmega16 device. * First Analog Comparator conversion may be delayed * Interrupts may be lost when writing the timer registers in the asynchronous timer * IDCODE masks data from TDI input 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices. Problem Fix/Workaround When the device has been powered or reset, disable then enable theAnalog Comparator before the first conversion. 2. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. Problem Fix/Workaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2 3. IDCODE masks data from TDI input The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR. Problem Fix / Workaround - - If ATmega16 is the only device in the scan chain, the problem is not visible. Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Issue the BYPASS instruction to the ATmega16 while reading the Device ID Registers of preceding devices of the boundary scan chain. If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the ATmega16 must be the fist device in the chain.
-
ATmega16(L) Rev. L
* First Analog Comparator conversion may be delayed * Interrupts may be lost when writing the timer registers in the asynchronous timer * IDCODE masks data from TDI input 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices. Problem Fix/Workaround When the device has been powered or reset, disable then enable theAnalog Comparator before the first conversion. 2. Interrupts may be lost when writing the timer registers in the asynchronous timer
15
2466NS-AVR-10/06
If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. Problem Fix/Workaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2 3. IDCODE masks data from TDI input The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR. Problem Fix / Workaround - - If ATmega16 is the only device in the scan chain, the problem is not visible. Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Issue the BYPASS instruction to the ATmega16 while reading the Device ID Registers of preceding devices of the boundary scan chain. If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the ATmega16 must be the fist device in the chain.
-
ATmega16(L) Rev. K
* First Analog Comparator conversion may be delayed * Interrupts may be lost when writing the timer registers in the asynchronous timer * IDCODE masks data from TDI input 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices. Problem Fix/Workaround When the device has been powered or reset, disable then enable theAnalog Comparator before the first conversion. 2. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. Problem Fix/Workaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2 3. IDCODE masks data from TDI input The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR. Problem Fix / Workaround - - If ATmega16 is the only device in the scan chain, the problem is not visible. Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from
16
ATmega16(L)
2466NS-AVR-10/06
ATmega16(L)
succeeding devices of the scan chain. Issue the BYPASS instruction to the ATmega16 while reading the Device ID Registers of preceding devices of the boundary scan chain. - If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the ATmega16 must be the fist device in the chain.
ATmega16(L) Rev. J
* First Analog Comparator conversion may be delayed * Interrupts may be lost when writing the timer registers in the asynchronous timer * IDCODE masks data from TDI input 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices. Problem Fix/Workaround When the device has been powered or reset, disable then enable theAnalog Comparator before the first conversion. 2. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. Problem Fix/Workaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2 3. IDCODE masks data from TDI input The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR. Problem Fix / Workaround - - If ATmega16 is the only device in the scan chain, the problem is not visible. Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Issue the BYPASS instruction to the ATmega16 while reading the Device ID Registers of preceding devices of the boundary scan chain. If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the ATmega16 must be the fist device in the chain.
-
ATmega16(L) Rev. I
* First Analog Comparator conversion may be delayed * Interrupts may be lost when writing the timer registers in the asynchronous timer * IDCODE masks data from TDI input 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices. Problem Fix/Workaround When the device has been powered or reset, disable then enable theAnalog Comparator before the first conversion. 17
2466NS-AVR-10/06
2. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. Problem Fix/Workaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2 3. IDCODE masks data from TDI input The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR. Problem Fix / Workaround - - If ATmega16 is the only device in the scan chain, the problem is not visible. Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Issue the BYPASS instruction to the ATmega16 while reading the Device ID Registers of preceding devices of the boundary scan chain. If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the ATmega16 must be the fist device in the chain.
-
ATmega16(L) Rev. H
* First Analog Comparator conversion may be delayed * Interrupts may be lost when writing the timer registers in the asynchronous timer * IDCODE masks data from TDI input 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices. Problem Fix/Workaround When the device has been powered or reset, disable then enable theAnalog Comparator before the first conversion. 2. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. Problem Fix/Workaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2 3. IDCODE masks data from TDI input The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR. Problem Fix / Workaround - If ATmega16 is the only device in the scan chain, the problem is not visible.
18
ATmega16(L)
2466NS-AVR-10/06
ATmega16(L)
- Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Issue the BYPASS instruction to the ATmega16 while reading the Device ID Registers of preceding devices of the boundary scan chain. If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the ATmega16 must be the fist device in the chain.
-
19
2466NS-AVR-10/06
Datasheet Revision History
Rev. 2466N-10/06
Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 1. Updated "Timer/Counter Oscillator" on page 31. 2. Updated "Fast PWM Mode" on page 102. 3. Updated Table 38 on page 83, Table 40 on page 84, Table 45 on page 112, Table 47 on page 113, Table 50 on page 129 and Table 52 on page 130. 4. Updated C code example in "USART Initialization" on page 150. 5. Updated "Errata" on page 343.
Rev. 2466M-04/06
1. Updated typos. 2. Updated "Serial Peripheral Interface - SPI" on page 136. 3. Updated Table 86 on page 222, Table 116 on page 279 ,Table 121 on page 298 and Table 122 on page 300.
Rev. 2466L-06/05
1. Updated note in "Bit Rate Generator Unit" on page 179. 2. Updated values for VINT in "ADC Characteristics" on page 300. 3. Updated "Serial Programming Instruction set" on page 279. 4. Updated USART init C-code example in "USART" on page 145.
Rev. 2466K-04/05
1. Updated "Ordering Information" on page 11. 2. MLF-package alternative changed to "Quad Flat No-Lead/Micro Lead Frame Package QFN/MLF". 3. Updated "Electrical Characteristics" on page 294.
Rev. 2466J-10/04 Rev. 2466I-10/04
1. Updated "Ordering Information" on page 11. 1. Removed references to analog ground. 2. Updated Table 7 on page 28, Table 15 on page 38, Table 16 on page 42, Table 81 on page 211, Table 116 on page 279, and Table 119 on page 296. 3. Updated "Pinout ATmega16" on page 2. 4. Updated features in "Analog to Digital Converter" on page 205. 5. Updated "Version" on page 230. 6. Updated "Calibration Byte" on page 264.
20
ATmega16(L)
2466NS-AVR-10/06
ATmega16(L)
7. Added "Page Size" on page 265.
Rev. 2466H-12/03 Rev. 2466G-10/03
1. Updated "Calibrated Internal RC Oscillator" on page 29. 1. Removed "Preliminary" from the datasheet. 2. Changed ICP to ICP1 in the datasheet. 3. Updated "JTAG Interface and On-chip Debug System" on page 36. 4. Updated assembly and C code examples in "Watchdog Timer Control Register - WDTCR" on page 43. 5. Updated Figure 46 on page 103. 6. Updated Table 15 on page 38, Table 82 on page 218 and Table 115 on page 279. 7. Updated "Test Access Port - TAP" on page 223 regarding JTAGEN. 8. Updated description for the JTD bit on page 232. 9. Added note 2 to Figure 126 on page 255. 10. Added a note regarding JTAGEN fuse to Table 105 on page 263. 11. Updated Absolute Maximum Ratings* and DC Characteristics in "Electrical Characteristics" on page 294. 12. Updated "ATmega16 Typical Characteristics" on page 302. 13. Fixed typo for 16 MHz QFN/MLF package in "Ordering Information" on page 11. 14. Added a proposal for solving problems regarding the JTAG instruction IDCODE in "Errata" on page 15.
Rev. 2466F-02/03
1. Added note about masking out unused bits when reading the Program Counter in "Stack Pointer" on page 12. 2. Added Chip Erase as a first step in "Programming the Flash" on page 291 and "Programming the EEPROM" on page 292. 3. Added the section "Unconnected pins" on page 55. 4. Added tips on how to disable the OCD system in "On-chip Debug System" on page 34. 5. Removed reference to the "Multi-purpose Oscillator" application note and "32 kHz Crystal Oscillator" application note, which do not exist. 6. Added information about PWM symmetry for Timer0 and Timer2.
21
2466NS-AVR-10/06
7. Added note in "Filling the Temporary Buffer (Page Loading)" on page 256 about writing to the EEPROM during an SPM Page Load. 8. Removed ADHSM completely. 9. Added Table 73, "TWI Bit Rate Prescaler," on page 183 to describe the TWPS bits in the "TWI Status Register - TWSR" on page 182. 10. Added section "Default Clock Source" on page 25. 11. Added note about frequency variation when using an external clock. Note added in "External Clock" on page 31. An extra row and a note added in Table 118 on page 296. 12. Various minor TWI corrections. 13. Added "Power Consumption" data in "Features" on page 1. 14. Added section "EEPROM Write During Power-down Sleep Mode" on page 22. 15. Added note about Differential Mode with Auto Triggering in "Prescaling and Conversion Timing" on page 208. 16. Added updated "Packaging Information" on page 12.
Rev. 2466E-10/02 Rev. 2466D-09/02
1. Updated "DC Characteristics" on page 294. 1. Changed all Flash write/erase cycles from 1,000 to 10,000. 2. Updated the following tables: Table 4 on page 26, Table 15 on page 38, Table 42 on page 85, Table 45 on page 112, Table 46 on page 112, Table 59 on page 144, Table 67 on page 168, Table 90 on page 237, Table 102 on page 261, "DC Characteristics" on page 294, Table 119 on page 296, Table 121 on page 298, and Table 122 on page 300. 3. Updated "Errata" on page 15.
Rev. 2466C-03/02
1. Updated typical EEPROM programming time, Table 1 on page 20. 2. Updated typical start-up time in the following tables: Table 3 on page 25, Table 5 on page 27, Table 6 on page 28, Table 8 on page 29, Table 9 on page 29, and Table 10 on page 30. 3. Updated Table 17 on page 43 with typical WDT Time-out. 4. Added Some Preliminary Test Limits and Characterization Data. Removed some of the TBD's in the following tables and pages: Table 15 on page 38, Table 16 on page 42, Table 116 on page 272 (table removed in document review #D), "Electrical Characteristics" on page 294, Table 119 on page 296, Table 121 on page 298, and Table 122 on page 300. 5. Updated TWI Chapter.
22
ATmega16(L)
2466NS-AVR-10/06
ATmega16(L)
Added the note at the end of the "Bit Rate Generator Unit" on page 179. 6. Corrected description of ADSC bit in "ADC Control and Status Register A - ADCSRA" on page 220. 7. Improved description on how to do a polarity check of the ADC doff results in "ADC Conversion Result" on page 217. 8. Added JTAG version number for rev. H in Table 87 on page 230. 9. Added not regarding OCDEN Fuse below Table 105 on page 263. 10. Updated Programming Figures: Figure 127 on page 265 and Figure 136 on page 277 are updated to also reflect that AVCC must be connected during Programming mode. Figure 131 on page 273 added to illustrate how to program the fuses. 11. Added a note regarding usage of the "PROG_PAGELOAD ($6)" on page 283 and "PROG_PAGEREAD ($7)" on page 283. 12. Removed alternative algortihm for leaving JTAG Programming mode. See "Leaving Programming Mode" on page 291. 13. Added Calibrated RC Oscillator characterization curves in section "ATmega16 Typical Characteristics" on page 302. 14. Corrected ordering code for QFN/MLF package (16MHz) in "Ordering Information" on page 11. 15. Corrected Table 90, "Scan Signals for the Oscillators(1)(2)(3)," on page 237.
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2466NS-AVR-10/06
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2466NS-AVR-10/06

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